This invention relates to serial communications interfaces, and more particularly, to circuitry for synchronizing and deskewing multi-channel serial communications links between integrated circuits such as programmable logic devices.
Serial communications formats are often used in modern electronics systems. Serial communications can be faster than parallel communications, use fewer pins, and, particularly when differential signaling schemes are used, can have higher noise immunity.
It can be challenging to handle serial data streams at high data rates (e.g., at data rates above several Gbps). As a result, it is often advantageous to support high-speed serial data communications using multiple smaller serial data paths operating in parallel. For example, 10 Gbps Ethernet communications can be supported using four parallel 3.125 Gbps serial paths using a XAUI interface and an OC-192 SONET channel can be transmitted over four parallel OC-48 channels.
In a high-speed serial link composed of multiple lower-speed serial channels, each lower-speed channel is subject to a different environment due to variations in chip layouts, pin locations, signal paths, thermal conditions, etc. As a result of these different environments, signals travel over each of the lower-speed serial channels differently. At the receiving end of the link, the lower-speed parallel serial channels must be deskewed and synchronized.
Conventional arrangements for deskewing and synchronizing the lower-speed channels involve the use of two sets of first-in-first-out (FIFO) buffers. Data is first deskewed using deskewing FIFO and is then synchronized using synchronization FIFO.
A two-stage deskew-synchronization FIFO arrangement uses a fixed amount of FIFO resources for deskewing and for synchronization. The size of the deskew FIFO limits the amount by which the earliest-arriving channel can lead the latest-arriving channel. The size of the synchronization FIFO determines how much clock wander is permitted between the recovered clocks from each channel and the common clock used by the receiving circuit.
Both the deskew FIFO and the synchronization FIFO must have sufficient capacity to tolerate worst-case conditions. This tends to make the FIFOs large. Moreover, the sizes of conventional FIFOs are fixed, which can make conventional FIFO arrangements inflexible.